`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2020/11/09 09:30:41
// Design Name: 
// Module Name: flowlight_led
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module flowLED(
    input rst_n_i,
    input clk_i,  // 1hz
    input en_i,
    output [7:0] led_o
    );
    
    wire rst = ~rst_n_i;
    reg [2:0] cnt = 3'b000;
    
    always @(posedge clk_i or posedge rst) begin
        if (rst == 1'b1) begin
            cnt <= 3'b0;
        end else if (en_i == 1'b1) begin
            cnt <= (cnt>=7) ? 3'b0 : cnt+3'b1;
        end else begin
            cnt <= cnt;
        end
    end
    
    assign led_o[7] = (cnt==7) ? 1'b1 : 1'b0;
    assign led_o[6] = (cnt==6) ? 1'b1 : 1'b0;
    assign led_o[5] = (cnt==5) ? 1'b1 : 1'b0;
    assign led_o[4] = (cnt==4) ? 1'b1 : 1'b0;
    assign led_o[3] = (cnt==3) ? 1'b1 : 1'b0;
    assign led_o[2] = (cnt==2) ? 1'b1 : 1'b0;
    assign led_o[1] = (cnt==1) ? 1'b1 : 1'b0;
    assign led_o[0] = (cnt==0) ? 1'b1 : 1'b0;
    
endmodule
